In the integrated circuit (IC) industry, input buffer circuitry is fabricated on a periphery of an integrated circuit die and electrically connected between an external pin of the integrated circuit and internal circuitry within the IC. In essence, the input buffer circuitry is an interface between the internal IC circuitry and an external environment outside of the IC so that data can be communicated from the external environment into and out from the integrated circuit.
Integrated circuits (ICs) are routinely designed such that one integrated circuit in an electrical system operates at a first power supply voltage and a second integrated circuit operates using a different power supply voltage level. For example, a first common voltage supply in the industry is roughly a 5.0 volts, a second voltage supply used in the industry is roughly 3.3 volts, a third voltage commonly used in the industry is roughly 2.5 volts, and a fourth commonly used voltage supply level is roughly 1.8 volts where any electrical system may contain one or more devices operating at these voltage levels. As an example, a 5.0 volt part may need to interface to a 1.8 volt part wherein the input buffer that is used to communicate between these two parts must be able to handle the discrepancy in voltage while still rendering acceptable performance. Due to the fact that there are several different common power supply voltage levels which are readily available in the industry, communication between these different devices has become more complex. Input and/or output buffers must now ensure interoperability of these different devices while maintaining optimal performance, if possible. Therefore, the design of such buffers has become increasingly more difficult and increasingly more important in the IC industry.
FIG. 2 illustrates a conventional two stage input buffer 200 that is suitable for interfacing a circuit operating at a first voltage to a second integrated circuit operating at a second voltage. In this illustrated example, pad 105 receives a signal, e.g., a digital data signal with a high peak voltage of VDDPST from a high voltage circuit (not shown). The buffer 200 provides an output signal at a lower voltage at circuit pad 107, e.g., a digital signal with peak voltage at the lower operating voltage VDD of the integrated circuit. Level down circuit 210, which converts the higher voltage VDDPST to the lower voltage VDD, is essentially a two stage inverter circuit comprising transistors forming first inverter 220 and second inverter 230 coupled at node 225. In this prior art circuit, inverter 220 serves as an input threshold control buffer and inverter 230 provides the VDDPST to VDD level down operation. To reduce leakage current induced by the P/N MOS devices of inverters 220 and 230, the channel width of these devices are small. These inverters may not be able to provide sufficient driving current. Therefore, inverter 150′ acts as a buffer stage to provide sufficient driving current, thereby requiring inverter 150 to invert the signal provided by inverter 230 at node 235.
The two-stage interface shown in FIG. 2 requires devices having different oxide thicknesses. Transistors in inverters 220 and 230 require thick oxides that can operate at the higher voltages provided at pad 105, and stages 150 and 150′ utilize transistors having thinner gate oxides that operate at the lower voltage VDD. This dual gate oxide structure increases both the complexity and cost of the IC fabrication process, as additional mask structures and processing steps are required to provide the dual gate structure.
To reduce the fabrication cost and complexity, the input buffer should comprise only devices having thin oxide layers. Gate oxide reliability, however, is critical in an input buffer that includes only devices having thin oxides. All voltage drops (e.g., Vgs and Vgd) in a transistor should be less than the oxide breakdown voltage to ensure that the circuit can operate for a reasonable lifetime. FIG. 1 illustrates a prior art input buffer 100 that is commonly used in the integrated circuit industry that includes only thin oxide devices. The buffer of FIG. 1 is fabricated on an IC die and allows two integrated circuits with different power supply voltages to interface to one another. The integrated circuit incorporating the circuit 100 contains a chip pad 105 that is used to receive input data from external to the integrated circuit. An input signal provided to the chip pad/terminal 105 passes through a resistive element 112 and is communicated through an input pass transistor 114. The transistor 114 of FIG. 1 has a gate/control electrode that is coupled to the operating voltage VDD of the integrated circuit chip.
The transistor 114 ensures that the inverter input node 109 does not rise to a voltage level that can damage the transistors 118 and 120. Specifically, any voltage provided on the chip pad 105 through the resistor 112 will be limited at VDD-Vthn (the threshold voltage of transistor 114) when communicated through the transistor 114 making the voltage at the inverter node 109 less than VDDPST when VDDPST in FIG. 1 is greater than VDD. In short, transistor 114 protects the transistors 118 and 120 from a damaging overvoltage occurrence that may occur when an integrated circuit operating at a high power supply voltage is coupled to the integrated circuit operating at the low power supply voltage VDD.
The input signal initially provided through the chip pad 105 is then provided via the inverter input node 109 to the inverter comprising transistors 118 and 120. The inverter, comprising transistors 118 and 120, is connected to a ground potential and an internal VDD voltage. The VDD voltage is a voltage that is supplied to operate all the circuitry on the integrated circuit including the input buffer 100. Typically, VDD can be any voltage but is usually 2.5 volts, 1.8 volts, 1.5 volts, 1.2 volts, 1.0 volt or 0.8 volts in modem high performance low power microprocessors and memory. The inverter, comprising the transistors 118 and 120, buffers the input signal to node 130 with logical inversion. Because the input voltage at node 109 is limited to VDD−Vthn, the PMOS 118 is always on and leakage current can become a problem. PMOS transistor 116 is provided to ensure that the VDD to ground path can be turned off as VPAD exceeds VDD−|Vthp|, where Vthp is the threshold voltage of PMOS 116. The output voltage of level down inverter 110 is then inverted through the inverter 150 comprising transistors 152 and 154, thereby providing output voltage at the node 107 between 0−VDD from a 0−VDDPST signal applied at input node 105. This signal provided at node 107 is routed to functional circuitry (not shown) located within the integrated circuit containing the circuit 100 so that incoming information may be processed by the system.
The gate voltage of the transistors 118 and 120 is limited to VDD−Vthn. Consequently, the maximum Vgd and Vgs is less than VDD and no oxide stress is present in transistors 118 and 120 under all operating conditions. For transistor 116, the maximum Vgd and Vgs is VDDPST−VDD. No oxide degradation is encountered if VDDPST−VDD is less than the oxide breakdown voltage of PMOS 116.
While the circuit of FIG. 1 is commonly used and is an adequate input buffer in certain circumstances, the circuitry of FIG. 1 has several disadvantages. First, the inverter comprising transistors 118 and 120 is typically fixed to a trigger point that is very low relative to the peak-to-peak voltage received from pad 105. This trigger point is set to the threshold voltage of NMOS 120, e.g., 0.4–0.5 V. During the rising edge of the signal VPAD at pad 105, specifically between 0V and Vthn, both PMOS 116 and 118 are turned on. The output of stage 110 is VDD. When VPAD is greater than Vthn and less than VDD−|Vthp|, all transistors are on, and the voltage at node 130 goes from VDD to low. When VPAD exceeds VDD−|Vthp|, PMOS 116 turns off and the voltage at node 130 become 0V. This is not advantageous since the trigger point that is not roughly half way between VDDPST and ground and mismatched transistors are required to adjust the trigger point to within Vthn and VDD−|Vthp|.
To compensate for this noise margin problem, the transistors 118 and 120 can be fabricated with significantly different aspect ratios to statically fix the trigger point at yet another voltage value (e.g., 1.6 volts). This mismatching of the transistors 118 and 120 results in an imbalanced inverter that can have different operating characteristics when the inverter is transitioning from a high voltage to a low voltage and vice versa. Since timing constraints of external buses and the like are typically designed to the worse case transition, the mismatch in the transistors 118 and 120 that improves noise margins may impact the maximal speed at which the device can be operated.
As described above, the buffer circuit 100 suffers from a non-advantageous asymmetric transfer property and/or requires mismatched transistors. Therefore, there remains a need for a new single gate oxide input buffer, particularly a single gate oxide input buffer that eliminates or reduces this low threshold voltage problem.